#ifndef S_QSPI_REG_H
#define S_QSPI_REG_H

//device base addr
#define DEV_QSPI_00_BASE_ADDR    (0x43C00000U)
#define DEV_QSPI_01_BASE_ADDR    (0x43C00000U)
#define DEV_QSPI_02_BASE_ADDR    (0x43C00000U)
#define DEV_QSPI_03_BASE_ADDR    (0x43C00000U)
#define DEV_QSPI_04_BASE_ADDR    (0x43C00000U)
#define DEV_QSPI_05_BASE_ADDR    (0x43C00000U)
#define DEV_QSPI_06_BASE_ADDR    (0x43C00000U)
#define DEV_QSPI_07_BASE_ADDR    (0x43C00000U)
#define DEV_QSPI_08_BASE_ADDR    (0x43C00000U)
#define DEV_QSPI_09_BASE_ADDR    (0x43C00000U)
#define DEV_QSPI_10_BASE_ADDR    (0x43C00000U)
#define DEV_QSPI_11_BASE_ADDR    (0x43C00000U)
#define DEV_QSPI_12_BASE_ADDR    (0x43C00000U)
#define DEV_QSPI_13_BASE_ADDR    (0x43C00000U)
#define DEV_QSPI_14_BASE_ADDR    (0x43C00000U)
#define DEV_QSPI_15_BASE_ADDR    (0x43C00000U)

//address of target chip's top level buffers for qspi channels. they will be used in indirect read mode .
//the hardware design shows that every 2 qspi channels share the same top level buffer, so qspi00,qspi01 share the same buffer address. 
#define TOP_LEVEL_BUF_00_ADDR    (0x43F00000U) 
#define TOP_LEVEL_BUF_01_ADDR    (0x43F00000U) 
#define TOP_LEVEL_BUF_02_ADDR    (0x43F10000U)  
#define TOP_LEVEL_BUF_03_ADDR    (0x43F10000U)  
#define TOP_LEVEL_BUF_04_ADDR    (0x43F20000U)  
#define TOP_LEVEL_BUF_05_ADDR    (0x43F20000U)  
#define TOP_LEVEL_BUF_06_ADDR    (0x43F00000U)  
#define TOP_LEVEL_BUF_07_ADDR    (0x43F00000U)      
#define TOP_LEVEL_BUF_08_ADDR    (0x43F00000U)  
#define TOP_LEVEL_BUF_09_ADDR    (0x43F00000U)  
#define TOP_LEVEL_BUF_10_ADDR    (0x43F00000U)  
#define TOP_LEVEL_BUF_11_ADDR    (0x43F00000U)  
#define TOP_LEVEL_BUF_12_ADDR    (0x43F00000U)  
#define TOP_LEVEL_BUF_13_ADDR    (0x43F00000U)  
#define TOP_LEVEL_BUF_14_ADDR    (0x43F00000U)  
#define TOP_LEVEL_BUF_15_ADDR    (0x43F00000U)  

//IRQ device-tree path for each channel,maybe every 4 channels will share the same IRQ num in future.
#define QSPI_00_IRQ_DT_PATH          "/amba_pl/my_irq@0"
#define QSPI_01_IRQ_DT_PATH          "/amba_pl/my_irq@1"

//register addr
#define TX_G0_BASE_ADDR         (0x0U) //the base address of FIFO 0
#define TX_G1_BASE_ADDR         (0x100U) //the base address of FIFO 0
#define TX_ADDR_OFFSET          (0x00U) //28 bits target address of FIFO 0. 
#define TX_CTL_OFFSET           (0x04U) //transfer control register.
#define TX_STATUS_OFFSET        (0x08U) //transfer status register. 
#define TX_DATA_START_OFFSET    (0x20U) //there are 32 registers for data,this is the start offset. 

#define RX_BASE_ADDR            (0x200U)
#define RX_ADDR_OFFSET          (0x00U) //28 bits target address of FIFO 0. 
#define RX_CTL_OFFSET           (0x04U) //receive control register. 
#define RX_STATUS_OFFSET        (0x08U) //receive status register. 
#define RX_ADDR_ON_ECC_OFFSET   (0x0CU) //the address stored when an ECC error during reading.we can use this address to re-read. 
#define RX_INFO_ON_ECC_OFFSET   (0x10U) //the other info stored when an ECC error during reading.we can use them to re-read.. 
#define RX_ECC_CNT_OFFSET       (0x14U) //1bit ECC auto corrections count in receiving. 
#define RX_DATA_START_OFFSET    (0x20U) //the start register of read datas, there are 32 registers. 

#define INT_REG_BASE            (0x300)
#define INT_STATUS_OFFSET       (0)
#define INT_MASK_OFFSET         (0x4U)
#define INT_CLEAR_OFFSET        (0x8U) 

#define QSPI_RESET_REG          (0x30CU) //write 1 to bit0 make qspi ip core reset.

//bits in registers define
/*************   TX status register ******************/
#define TX_FIFO_EMPTY           (0x01<<1)
#define TX_FINISHED             (0x01<<0)

/*************   TX control register ******************/
#define TX_START_SEND           (0x01<<0)
#define TX_DATA_LEN_OFFSET      (8U) //TX data len need left shift TX_DATA_OFFSET .

/*************   TX/RX control register common ******************/
#define EN_ECC                  (0x01<<1)

/*************   RX control register ******************/
#define RX_DATA_LEN_OFFSET      (8U) //RX data len need left shift RX_DATA_OFFSET .
#define RX_CLR_2BIT_ECC_OFFSET  (7U)
#define RX_CLR_1BIT_ECC_OFFSET  (6U)
#define RX_DUMMY_CYCLE_OFFSET   (16U)
#define RX_INDIRECT_MOD_OFFSET  (2U)
#define RX_START_RCV            (1<<0)

/*************   RX status register ******************/
#define RX_DATA_ERR             (0x01<<2)
#define RX_FINISHED             (0x01)

/************ interrupt status register ****************/
#define NODE_INT                (0x01<<5)
#define TX_FIFO_1_FINISH_INT    (0x01<<4)
#define TX_FIFO_0_FINISH_INT    (0x01<<3)
#define RX_2BIT_ECC_INT         (0x01<<2)
#define RX_1BIT_ECC_INT         (0x01<<1)
#define RX_FINISH_INT           (0x01)

/************ interrupt mask register ****************/
#define DISABLE_NODE_INT                (0x01<<5)
#define DISABLE_TX_FIFO_1_FINISH_INT    (0x01<<4)
#define DISABLE_TX_FIFO_0_FINISH_INT    (0x01<<3)
#define DISABLE_RX_2BIT_ECC_INT         (0x01<<2)
#define DISABLE_RX_1BIT_ECC_INT         (0x01<<1)
#define DISABLE_RX_FINISH_INT           (0x01)

/************ interrupt status clear register ****************/
#define CLR_NODE_INT                (0x01<<5)
#define CLR_TX_FIFO_1_FINISH_INT    (0x01<<4)
#define CLR_TX_FIFO_0_FINISH_INT    (0x01<<3)
#define CLR_RX_2BIT_ECC_INT         (0x01<<2)
#define CLR_RX_1BIT_ECC_INT         (0x01<<1)
#define CLR_RX_FINISH_INT           (0x01)
/************ global control register ****************/
#define RESET_QSPI_MOD          (0x01)

#endif